The present invention relates to a flash memory device, and more particularly to a flash memory device having inter-gate plugs to prevent a mutual interference between cell gates.
In general, a NAND flash memory device includes a plurality of cell blocks. Each cell block contains cell strings in which a plurality of cells for storing data is connected in series. A drain select transistor is provided between the cell string and the drain, and a source select transistor is provided between the cell string and the source.
A method of manufacturing a flash memory device in the related art will be described in short below. An isolation structure is formed on a semiconductor substrate by a Shallow Trench Isolation (STI) process, defining an active region and a field region.
A tunnel oxide film having a predetermined thickness is formed on the active region. A polysilicon film is formed on the tunnel oxide film. The polysilicon film is used as a conductive layer for a floating gate. A dielectric film is formed on the polysilicon film. The dielectric film is formed by sequentially laminating an oxide film, a nitride film, and an oxide film, thereby forming an ONO layer.
A second polysilicon film is formed on the dielectric film. This polysilicon film is used as a conductive layer for a control gate and is formed so that it is common to a plurality of unit cells.
The control gate also includes tungsten silicide deposited on the second polysilicon film to reduce the resistivity of the control gate. A gate hard mask is deposited on the tungsten silicide and gate lines are formed by photolithography and etch processes. Semiconductor devices are continuously being miniaturized and highly integrated. Accordingly, a cell's threshold voltage Vt may vary when the neighboring cells are being programmed due to a mutual interference between the cell gates. Such the mutual interference becomes more significant as the cells are reduced in size, e.g., cells of 100 nanometers or less.